Low power design of vlsi circuits and systems
10 Citations•2009•
P. Zhao, Zhongfeng Wang
2009 IEEE 8th International Conference on ASIC
This paper first gives a brief overview for low power optimization techniques at system and architecture level, then focuses discussion on circuit level methods specifically state-of-the-art low power design techniques of clocking systems.
Abstract
Power consumption is the bottleneck of system performance and is listed as one of the top three challenges in ITRS 2008. Low power design can be exploited at various levels, e.g., system level, architecture level, circuit level, and device level. This paper first gives a brief overview for low power optimization techniques at system and architecture level, then focus discussion on circuit level methods specifically state-of-the-art low power design techniques of clocking systems.