Design of Low Power Logic Gates for VLSI Design Circuits
88 Citations•2023•
Telagamalla Gopi
International Journal of Science and Research (IJSR)
NAND and NOR gates realized, stacking technique consumes low power than standard reduction techniques, and circuits are simulated in Tanner EDA Tool with Generic 250 nm transistors.
Abstract
High power consumption has become key role in VLSI design circuits, when it comes in battery operated applications such that to save the battery life. Short circuit power and switching power play key role in power dissipations, there are so many techniques to reduce power. By stacking arrangement, we can reduce power and we can utilize technique for various circuits. In this paper NAND and NOR gates realized, stacking technique consumes low power than standard reduction techniques. These circuits are simulated in Tanner EDA Tool with Generic 250 nm transistors.