Impact of Technology Scaling on Low Power VLSI CMOS Design

Abstract

Many factors are important in optimizing MOS transistor performance. Gate oxide thickness should be as thin as possible to improve short channel characteristics, maximize the drain current, and facilitate supply voltage scaling for reduces power. The minimum gate oxide thickness is dedicated by reliability, defect density, and gate capacitance considerations. Threshold voltage should also be set low to maximize the drain current and to facilitate the reduced supply voltage, but not low as to increase the OFF current and standby power to unacceptable levels or to result in functional failure of dynamic circuits. The performance enhancement for each new technology will generally decrease with each new generation of technology. CPL performance degrades much faster than other logic styles because of the reduction of the ration Vdd/Vth in technology scaling. Hot carrier effect makes it even worse by increasing Vth over the long term. CPL area tends to grow up, increasing power dissipation and area. Domino’s performance and power deteriorates, because of leakage and contention caused by the keeper transistor. CCVS is also affected by leakage power, but it does not have any contention problems during evaluation. Because interconnects are not scaled linearly with technology, the performance of power consumed in the clock tree increases.