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Logical Effort: Designing Fast CMOS Circuits, Ivan E. Sutherland, Robert F. Sproull, and David Harris (Morgan Kaufmann, San Francisco, Calif., 1999, 240 pp., ISBN 155860-557-6, www.mkp.com, $42.95) Ivan Sutherland is the recipient of both the ACM Turing Award and the IEEE Von Neumann Medal. He and Bob Sproull are Sun fellows (and vice presidents). Both are highly acclaimed experts in the design of graphics hardware and software. They published the theoretical kernel of this book in a paper in 1991. David Harris teaches engineering at Harvey Mudd College. After developing many of the same techniques independently, he persuaded Sutherland and Sproull to let him rework their unpublished notes into this book. Logical effort is a theoretical construct that measures the relative cost of computation inherent in the circuit topology that implements a logic gate’s function. A logic gate may contain many transistors, and MOS transistors in series conduct electricity relatively poorly. Thus, some logic gates require substantially more logical effort than others. Electrical effort is the ratio of the logic gate’s output to input capacitances. The product of logical effort and electrical effort, plus a term that represents the parasitic capacitance of the logic gate, gives a relative measure of the time it takes a signal to pass through the logic gate. Because input capacitance depends largely on the sizes of the transistors that make up the logic gate, this analysis allows the authors to decompose signal delays into separate logical, transistor size, output load, and parasitic terms. The authors recognize that this is an approximation, but it is a useful one. It allows them, through relatively elementary mathematics, to arrive quickly at circuit designs that they can prove are close to optimal speed. The authors know that many good circuit designers have independently discovered some of their results, and they acknowledge that there are many heuristics that produce good results. Nonetheless, many designers—especially beginners—rely on the “simulate and tweak” method, and for those designers, the authors’ method is a big improvement. As Sutherland says about the original work he did on this method in 1985,