A Low Power Digital Binary Magnitude Comparator Design for Very Large Scale Integration Applications
Two designs of low power digital binary magnitude comparator based on static complementary CMOS logic style based on recently reported latest XNOR gate designs are reported, highly suitable for VLSI applications.
Abstract
This paper reports two designs of low power digital binary magnitude comparator based on static complementary CMOS logic style. The designs make use of recently reported latest XNOR gate designs. The comparator designs proposed here are easily scalable for higher order bits and thus highly suitable for VLSI applications. Mathematical equations establishing the relation between input bit width and transistor count of the magnitude comparators have also been derived in this paper. For a 64 bit magnitude comparator, the designs proposed in this paper outperform an existing design by 12.17% and 10.42% in terms of transistor requirement and 14.81% and 11.78% in terms of average power consumption.