This thesis proposes to reduce the complexity of the design problem and the design time by using a high-level language to specify only the behavioral aspects of a circuit.
Abstract : Designing very large-scale integrated circuits requires several months or more and increases as the complexity of the design increases. This thesis proposes to reduce the complexity of the design problem and to reduce the design time by using a high-level language to specify only the behavioral aspects of a circuit. The circuit is then synthesized from this specification. Keywords include: Silicon compilation; VLSI circuit design; Synthesis; Computer-aided design; Logic minimization; PLA generation; Placement; Routing; Layout; and Integrated circuits.