A REPORT ON LOW POWER VLSI CURCUIT DESIGN
A new family of logic styles called preset Skewed Static Logic (PSSL) is proposed, which bridges the gap between the two main logic styles, static CMOS logic and domino logic, occupying an intermediate region in the energy-delay-robustness space between the two.
Abstract
We survey state-of-the-art optimization methods that target low power dissipation in VLSI circuits. The most important factor in any system design is power. Low power became a major factor where power dissipation has become as important consideration as performance and their area so there is a need of low power. We propose a new family of logic styles called preset Skewed Static Logic (PSSL). PSSL bridges the gap between the two main logic styles, static CMOS logic and domino logic, occupying an intermediate region in the energy-delay-robustness space between the two.. This paper reviews various known strategies and methodologies for designing low power circuits. This paper explains the relation between scaling, power consumption and design robustness.