Low power VLSI CMOS circuit design
In this presentation, several novel high performance digital circuit designs that emphasize low-power and low-voltage operation are introduced and utilize a wide range of techniques that are used in state-of-the-art VLSI systems and hence serve as good examples for low- power design.
Abstract
Summary form only given. The scaling of the CMOS channel length to below 0.5 /spl mu/m and increase of the chip density to the ULSI range have placed power dissipation on an equal footing with performance as a figure of merit in digital circuit design. Portability and reliability have also played a major role in the emergence of low-power, low-voltage, digital circuit designs. The need to extend the battery life, to have inexpensive packaging and cooling systems, and to reduce the weight and size of the equipment were the driving forces in this regard. Reducing the power dissipation of arithmetic operations while keeping the performance unaffected, is indispensable for digital signal processing (DSP), reduced instruction set computers (RISCs), microprocessors, etc. In this presentation, several novel high performance digital circuit designs that emphasize low-power and low-voltage operation are introduced. These circuits utilize a wide range of techniques that are used in state-of-the-art VLSI systems and hence serve as good examples for low-power design. In addition, important features of submicron VLSI technologies that support low-power operation of digital systems are discussed.