DESIGN TECHNIQUES FOR LOW POWER VLSI DESIGN

Abstract

With the advancement in VLSI technology and shrinking of the devices, power dissipation has emerged as an important factor while considering performance and area for VLSI Chip design. The need of low power VLSI design has become highly important, for portable applications. As the complexity of the chips is increasing day by day, the difficulty in limiting the power dissipation may limit the functionality of the computing systems. For the recent CMOS feature sizes, leakage power dissipation has also become an overriding feature for VLSI circuit designers. Power dissipation occurs at all the levels of abstraction like system level, architecture level, circuit level and physical level. In thision like system level, architecture level, circuit level and physical level. In this paper the author has identified many low power strategies and techniques to override these