A Survey of Design of RBS for Low Power VLSI
There is no any universal method to design to avoid tradeoff between delay, power consumption and complexity of the circuit, so the designer is required to opt appropriate technology for satisfying product need and applications.
Abstract
With the rapid growth of the portable electronic equipment, wearable computers, laptops, cell phones etc. the demand of the low power very large scale integration (VLSI) is dynamically increasing. The power consumption is one of the top most crucial limiting factors of the concern for the designing of the low power electronic circuits for the today’s & even before this era. The numbers of scientists/ researchers are struggling for overcoming such a limiting factor/ obstacle and proposing different ideas and designing methods from the logical level (Gate Level) to circuitry level (Physical level) and above for the very large scale integration Even after of such a struggle, there is no any universal method to design to avoid tradeoff between delay, power consumption and complexity of the circuit. Still, the designer is required to opt appropriate technology for satisfying product need and applications