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Survey of low power techniques for VLSI design

DOI: 10.1109/ICISS.1996.552423Semantic Scholar

10 Citations•1996•

E. de Angel, E. Swartzlander

1996 Proceedings. Eighth Annual IEEE International Conference on Innovative Systems in Silicon

The techniques presented in this paper have been implemented in modified-Booth multipliers and have been designed in 0.6 /spl mu/m technology and simulated in PowerMill.

Abstract

This paper presents a survey of low power techniques for digital circuits. The techniques presented in this paper have been implemented in modified-Booth multipliers. The multipliers have been designed in 0.6 /spl mu/m technology and simulated in PowerMill.