Analysis of Power Dissipation & Low Power VLSI Chip Design
This paper presents various techniques to reduce the power requirement in various stages of CMOS designing i.e. Dynamic Power Suppression, Adiabatic Circuits, Logic Design for Low Power, Reducing Glitches, Logic Level Power Optimization, Standby Mode Leakage Suppression.
Abstract
Low power requirement has become a principal motto in today’s world of electronics industries. Power dissipation has becoming an important consideration as performance and area for VLSI Chip design. With reducing the chip size, reduced power consumption and power management on chip are the key challenges due to increased complexity. Low power chip requirement in the VLSI industry is main considerable field due to the reduction of chip dimension day by day and environmental factors. For many designs, optimization of power is important as timing due to the need to reduce package cost and extended battery life. This paper present various techniques to reduce the power requirement in various stages of CMOS designing i.e. Dynamic Power Suppression, Adiabatic Circuits, Logic Design for Low Power, Reducing Glitches, Logic Level Power Optimization, Standby Mode Leakage Suppression, Variable Body Biasing, Sleep Transistors, Dynamic Threshold MOS, Short Circuit Power Suppression. Keywords-Low power, VLSI, CMOS, package cost, battery life, power dissipation.