Stat-LRC: statistical rules check for variational lithography
A methodology to perform Statistical Lithography Rules Check (Stat-LRC) involving design yield based on interconnect linewidth distribution for variation in lithographic input error sources is described and yield recovery improvement has been demonstrated.
Abstract
As interconnect densities increase with each technology generation, the lithographic processes required to print all features with acceptable irregularities have become more complex. Restricted design rules (RDR) and modelbased Design for Manufacturability (DFM) guidelines have been added to the existing Design Rule Check (DRC) software to prevent unprintable patterns to be drawn on the mask by predicting their imprint on the wafer. It is evident from analyses of predicted patterns that edge placement errors have a continuous distribution, hence a pass/fail cut-off is somewhat arbitrary. In this paper, we describe a methodology to perform Statistical Lithography Rules Check (Stat-LRC) involving design yield based on interconnect linewidth distribution for variation in lithographic input error sources. In this scheme, a list of error locations indicating polygons that have yield below a user specified threshold are listed. The overall design yield is recovered by trading-off slightly poorer EPE distributions for lines with short runs with excellent ones. The simulation/analysis environment is fully automated and yield recovery improvement has been demonstrated.