ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
Modified decoding algorithms for DS codes are proposed that provide error detection when the number of correctable bit errors is exceeded by one and combined error detection and correction capability of the modified decoder are provide.
Abstract
Modified decoding algorithms for DS codes are proposed that, in addition to error correction, provide error detection when the number of correctable bit errors is exceeded by one. This combined error detection and correction capability of the modified decoder are provide to prevent soft errors from causing data corruption, memories are typically protected with error correction codes (ECCs). Memory applications require low latency encoders and decoders. These codes allow us to design a fault tolerant error-detector unit that detects any error in the received code-vector despite having faults in the detector circuitry. The fault secure detector unit to check the output vector of the encoder and corrector circuitry, and if there is any error in