A Survey on Low Power High Speed Domino Circuit in Low Power VLSI Design

Abstract

Increased number of transistor count and reduced device size is main reason behind scaling and this incorporates leakage current also in other hand battery technology is growing very slowly hence we need low power circuit so that we can enhance overall performance of device. After evolution of CMOS circuit the scientist moved on static and dynamic circuit design. In static CMOS there are various limitations like no. of transistor count, power dissipation, slow speed, hence to overcome these limitation a new circuit pseudo NMOS is used. It exist somewhere between static and dynamic circuit. We have seen that FinFET technology is simulated by BISM4 model using HSPICE at 32nm process technology at 250C with CL=1pF at 100MHz frequency. When CMOS is compared with FinFET for 8 and 16 input OR gate we save average power 15.46%, 21.34% SFLD, 57.37%, 20.12% HSD, 30.90%, 42.46% CKD respectively.