Home / Papers / VLSI (Very Large Scale Integrated) Design of a 16 Bit...

VLSI (Very Large Scale Integrated) Design of a 16 Bit Very Fast Pipelined Carry Look Ahead Adder.

88 Citations1983
J. R. Conradi, B. R. Hauenstein
journal unavailable

This thesis is an introduction to the use of computer-aided design tools for the design of very large scale integrated circuits (VLSI) and a tutorial is given which illustrates their use in the computing environment at the Naval Postgraduate School.

Abstract

Abstract : This thesis is an introduction to the use of computer-aided design (CAD) tools for the design of very large scale integrated circuits (VLSI). The techniques are described and a tutorial is given which illustrates their use in the computing environment at the Naval Postgraduate School. The CAD tools were applied to design a 16-bit fast pipelined adder. (Author)