Design and Analysis of Various Standard Multipliers Using Low Power Very Large Scale Integration (VLSI)
This paper presents a comparative study of Field Programmable Gate Array implementation of standard multipliers using Verilog HDL, finding significant reduction in FPGA resources, delay, and power can be achieved using Reduced Wallace multipliers with Koggestone adder instead of standard parallel multipliers.
Abstract
This paper presents a comparative study of Field Programmable Gate Array (FPGA) implementation of standard multipliers using Verilog HDL. Multiplier is a good candidate for digital signal processing (DSP) applications such as finite impulse response (FIR) and discrete cosine transforms (DCT) and so on. Significant reduction in FPGA resources, delay, and power can be achieved using Reduced Wallace multipliers with Koggestone adder instead of standard parallel multipliers.