Top Research Papers on Low Power VLSI Design

This paper presents a comparative study of Field Programmable Gate Array implementation of standard multipliers using Verilog HDL, finding significant reduction in FPGA resources, delay, and power can be achieved using Reduced Wallace multipliers with Koggestone adder instead of standard parallel multipliers.

According the design flow of VLSI and the working mechanism of the microprocessor, a survey of low power design methodology at five levels such as system, behavioral, architectural, logic and physical levels is presented.

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Two designs of low power digital binary magnitude comparator based on static complementary CMOS logic style based on recently reported latest XNOR gate designs are reported, highly suitable for VLSI applications.

In this paper the author has identified many low power strategies and techniques to override these at all the levels of abstraction like system level, architecture level, circuit level and physical level.

The various causes of power dissipation in VLSI chips are discussed, and all the strategies and methodologies that can be applied for low power designing are reviewed.

The various strategies, methodologies and power management techniques for low power circuits and systems, and future challenges that must be met to designs low power high performance circuits are discussed.

The many issues facing designers at architectural, logic, circuit and device levels are described and some of the techniques that have been proposed to overcome these difficulties are presented.

The recent trends in the developments and advancements in the area of low power VLSI Design are surveyed in this paper.

The metrics and techniques used to assess the merits of the various solutions proposed for improved energy efficiency are presented and the trends and research topics for the future are concluded.

This work focuses on a new CMOS logic family called ADIABATIC LOGIC, based on the adiabatic switching principle, which dramatically reduces the power dissipation.

The main contribution of this research was the discovery of TSEL, the first true single phase energy recovering circuit family, which achieves very efficient operation in comparison with conventional CMOS and other energy recovering circuits.

The low power vlsi design and technology is universally compatible with any devices to read and is available in the digital library an online access to it is set as public so you can download it instantly.

Introduction to low-power VLSI design, G. Yeap and A. Wild low power design of off-chip drivers and transmission lines - a branch and bound approach, R. Gupta et al a new CMOS driver model for transient analysis and power dissipation analysis, H. Liao et al on the optimal drivers of high-speed low power ICs, D. Zhou and X.Y. Liu floorplan design with low power considerations, K.Y. Chao and D.F. Wong retiming sequential circuits for low power, J. Monteiro et al.

The basic notion and correlative factors of the circuit power are explained, and the design technology for low power VLSI is introduced on the base of the correlative Factors.

A novel common vdd and gnd technique is proposed to overcome the semiconductor leakage and this technique has excellent tradeoffs between power, delay and area, moreover this method will be new weapon for low power VLSI circuit designer.

Gate oxide thickness should be as thin as possible to improve short channel characteristics, maximize the drain current, and facilitate supply voltage scaling for reduces power.

The utility model relates to a dormant tube domino circuit used for a low power consumption VLSI (very-large-scale integration), which comprises a signal input end, signal output end, a clock signal end, the source electrode of the NMOS dormant tube is connected with an output end and the substrates of all NMOS tubes are connected with the ground voltage.

Very large scale integrated circuits are difficult to test once fabricated, due to the large number of internal circuit nodes that are not accessible as probe points, and the small number of primary inputs and outputs available to exercise and observe these internal nodes.

This paper surveys contemporary optimization techniques that aims low power dissipation in VLSI circuits to reduce the package cost and extended battery life.

A literature review upon the strategies and methodologies in designing low power VLSI systems is presented and it is suggested that the current generation of electronic design scenario demands low power architectures.

Low-Power circuit designs are the major requirements in today's electronic scenarios and means low complexity, time-saving methodology and provides good backup needs, which supports many portable devices to operate with enhanced power and good-in-operation for long-time without any interruptions.

Simulation results show the validity of the proposed techniques is effective to save power dissipation and to increase the speed of operation of the circuits to a large extent.

Recent development and progress in low power design, power estimation and optimization approaches, power optimization tools, and low power test were discussed in detail in order to provide some valuable reference for related research and design.

A passive compensation scheme for improving the signal quality over long metal interconnects is proposed, and the design of cyclic shifter is revisited by introducing two orthogonal new techniques: fanout splitting and cell order optimization using Integer Linear Programming.

A new family of logic styles called preset Skewed Static Logic (PSSL) is proposed, which bridges the gap between the two main logic styles, static CMOS logic and domino logic, occupying an intermediate region in the energy-delay-robustness space between the two.

In this presentation, several novel high performance digital circuit designs that emphasize low-power and low-voltage operation are introduced and utilize a wide range of techniques that are used in state-of-the-art VLSI systems and hence serve as good examples for low- power design.

The problem of optimizing the two-level representation of a Boolean function in order to minimize power consumption in PLAs is studied and it is proved that a minimum power solution for dynamic PLAs consists only of prime implicants of the function.

The various strategies, methodologies and power management techniques for low power circuits and systems, and future challenges that must be met to designs low power high performance circuits are discussed.

The performance analysis of Wallace-tree, Array and Baugh-Wooley multiplier architectures is carried out and Delay and Power dissipation of Wallace Tree multiplier is least whereas Array multiplier is a best for reduced area applications but not speed.

There is no any universal method to design to avoid tradeoff between delay, power consumption and complexity of the circuit, so the designer is required to opt appropriate technology for satisfying product need and applications.

The techniques presented in this paper have been implemented in modified-Booth multipliers and have been designed in 0.6 /spl mu/m technology and simulated in PowerMill.

The recent trends in the developments and advancements in the area of low power VLSI Design are surveyed in this paper.

This paper is on the comparative study of the current best domino logic methods using FinFETs and the unity noise gain for SCDNDTDL is 3.77X higher than the SG FinFet logic.

This paper first gives a brief overview for low power optimization techniques at system and architecture level, then focuses discussion on circuit level methods specifically state-of-the-art low power design techniques of clocking systems.

The various strategies, methodologies and power management techniques for low power circuits and systems are described and future challenges that must be met to designs low power high performance circuits are discussed.

Low--Power CMOS VLSI Design and Test of Low--Voltage CMOS Circuits and Low--Energy Computing Using Energy Recovery Techniques.

This framework depicts about the diverse systems, approaches and in addition control organization plans for low power circuits and structures and ensures that the cos lessening and versatility of gadget with appropriate power administration plans are ensured.

Various low leakage power design techniques to achieve low power dissipation are reviewed and various methods to reduce leakage power are reviewed.

This survey paper describes the various strategies, methodologies and power management techniques for low power VLSI circuits and future challenges that must be met by designers to designs low power high performance circuits are discussed.

Asynchrobatic Logic is a novel low-power design style that combines the energy saving benefits of asynchronous logic and adiabatic logic to produce systems whose power dissipation is reduced in several different ways.

In deep submicron technologies, leakage power becomes a key for a low power design due to its ever increasing proportion in chip’s total power consumption. Power dissipation is an important consideration in the design of CMOS VLSI circuits. High power consumption leads to reduction in battery life in case of battery powered applications and affects reliability packaging and cooling costs. We propose a technique called LCPMOS for designing CMOS gates which significantly cuts down the leakage current without increasing the dynamic power dissipation. LCPMOS, a technique to tackle the leakage prob...

A low power CMOS temperature sensor with digital output is presented in this work. The sensor is current based, the combination of dependent and independent current that control the frequency of 2 ring oscillators. The difference in frequency of this two ring oscillator is converted into a digital temperature code by asynchronous counters. The reference current and the PTAT current is generated by applying a temperature dependent voltage across two resistors with different temperature coefficients. To achieve a low power consumption, the temperature voltage reference operates under 200 mV and ...

This paper presents various techniques to reduce the power requirement in various stages of CMOS designing i.e. Dynamic Power Suppression, Adiabatic Circuits, Logic Design for Low Power, Reducing Glitches, Logic Level Power Optimization, Standby Mode Leakage Suppression.

A 8-bit 5GS/s streak simple to-advanced converter (ADC) is composed and reproduced in a 0.18μm CMOS innovation to bring about fast low power operation.

NAND and NOR gates realized, stacking technique consumes low power than standard reduction techniques, and circuits are simulated in Tanner EDA Tool with Generic 250 nm transistors.

A 8-bit 3 Gs/sec blaze simple to-advanced converter (ADC) in 45nm CMOS innovation is exhibited for low power and fast framework on-chip (Soc) applications.

FinFET technology is simulated by BISM4 model using HSPICE at 32nm process technology at 250C with CL=1pF at 100MHz frequency and CMOS is compared with FinFET for 8 and 16 input OR gate to save power.

A NOVEL NMOS and PMOS which has superior performance than conventional PMOS and NMOS, the design and performance checked at 90 nm, 180 nm and 45 nm technology and calculate the performance values.

During the period covered by the grant, two books and ten research papers were written under grant sponsorship, and nineteen of the researchpapers were written and published in conference proceeding.