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Low-Power SAR ADC Design: Overview and Survey of State-of-the-Art Techniques

DOI: 10.1109/tcsi.2022.3166792Source

126 Citations•2022•

Xiyuan Tang, Jiaxin Liu, Yi Shen

IEEE Transactions on Circuits and Systems I Regular Papers

A comprehensive survey of state-of-the-art low-power design techniques for every circuit block in the SAR ADC, including comparator, capacitive digital-to-analog converter (DAC), and SAR logic.

Abstract

This paper presents an overview for low-power successive approximation register (SAR) analog-to-digital converters (ADCs). It covers the operation principle, error analysis, and practical design issues. Furthermore, this paper provides a comprehensive survey of state-of-the-art low-power design techniques for every circuit block in the SAR ADC, including comparator, capacitive digital-to-analog converter (DAC), and SAR logic. The goal of this paper is to provide a useful overview to SAR ADC designers who want to improve the energy efficiency targeting low-to-medium speed applications.