Top Research Papers on VLSI

PAPs are used as the baseline for the discussion of signal processing engines and are about to do to the conventional signal processors what microprocessors and PAPs did to mainframes.

The IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) systems is published as a monthly journal under the co-sponsorship of the IEEE Circuits and Systems Society, the IEEE Computer Society, and the IEEE Solid-State Circuits Society.

The Circuits and Systems Society is an association of IEEE members with professional interest in the field of circuits and systems theory and member copies of Transactions/Journals are for personal use only.

The IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS is published as a monthly journal under the co-sponsorship of the IEEE Circuits and Systems Society, the IEEE Computer Society, and the IEEE Solid-State Circuits Society. All members of the IEEE are eligible for membership in all three societies upon payment of membership fee. Current society membership fees are: Circuits and Systems Society-$22, Computer Society $60, and Solid-State Circuits-$22. For information on joining, visit the IEEE website at https://www.ieee.org/membership/join/index.html ?WT.mc id=hc join or write t...

This paper surveys several common computer networking approaches and presents a novel concept, the Gatlinburg Rings, which is shown to be attractive for large networks.

A practical algorithm for fault simulation which simultaneously determines all detectable S-A faults for every gate in the circuit tree C, which requires only the evaluation of a circuit FS(C) which has equal to or less than 3(d+1), when d is the depth of C.

A synthesis algorithm finds a cascade of Toffoli and Fredkin gates with no backtracking and minimal look-ahead, and applies transformations that reduce the size of the circuit through template matching.

A family of "smart sensors" based on a micro - signal processor technique capable of identifying, detecting, and/or classifying particular target signatures in real - time with a high degree of reliability and flexibility while meeting system constraints of low cost, small size, and very low power dissipation is described.

This paper shows how one such system, a very high performance digital filter, is implemented using current technology.

This work is directed at obtaining special purpose structures for DSP tasks that are well suited for VLSI implementation.

This project is to establish, within a university research environment, a facility for the rapid execution of mask generation, wafer fabrication, and functional testing of user- generated custom I.C. designs.

A description is given of the various phases involved in reliability prediction model development, such as; literature collection/review, investigation of failure modes, failure rate data collection, statistical analysis methodologies, model factors quantification, and model validation.

A high—performance, cost—effective silicon—on—insulator (SOI) technology would have important near—term applications in radiation—hardened electronics and longer term applications in submicrometer VLSI. The advantages of SOI over bulk Si technology for these applications will be outlined, and CMOS, CJFET, andbipolar device structures being developed for SOI will be discussed. The current status and future prospects of the two most promising SOI technologies —— beam recrystallization and high—dose oxygen implantation —— will be reviewed, with emphasis on such issues critical to commercializatio...

During the period covered by the grant, two books and ten research papers were written under grant sponsorship, and nineteen of the researchpapers were written and published in conference proceeding.

This research presents an evolutionary computation algorithm for defect detection based on defective current and voltage considered based on various sizes and location of resistors, frequencies or voltage supply magnitudes using Genetic Algorithm.

A synthesis algorithm finds a cascade of Toffoli and Fredkin gates with no backtracking and minimal look-ahead, and applies transformations that reduce the size of the circuit through template matching.

An overview on architectures for VLSI implementations of video compression schemes as specified by standardization committees of the ITU and ISO, focussing on programmable architectures on heterogeneous and heterogeneous processor architectures is presented.

This paper will discuss one of the more advanced automated systems available, the TRE 800 SLR, and its engineering evaluation in the fabrication of VLSI circuits and emphasis will be placed on overlay accuracy including field-by-field registration, matching of steppers and mixing with other aligners.

This paper proposes a new design of 2T AND gate and performance comparison of proposed gate with existing 2T GDI technique is presented to prove the superiority of proposed design over existing 2T gate design.

Abstract : The test methods of MIL-STD-883 were reviewed to assess their appropriateness in view of the new package styles and materials being used for BLSI/VHSIC devices. Experiments were performed to judge the effectiveness of existing tests. Changes to existing tests are proposed where deemed necessary and new tests are developed where no existing method adequately assess new technology devices. Proposed changes and/or new package tests evaluate: solderability of leads; pin grid lead pull strength; leadless chip carrier bond strength; die attach bond analysis; characteristic impedance, capa...

A new approach is described for the automatic detection of defects in VLSI circuit patterns such as photomasks and wafers based on morphological feature extraction using templates that represent a set of local pixel configurations within a specified window.

Criteria and procedures that provide assurance as to a manufacturer's ability to provide functionally reproducible and reliable devices are desirable prior to user commitment to the design of a custom device. Additions and modifications to current practices are necessary when procurement of small batches of high-density, custom microelectronic devices are anticipated. This paper analyzes the problems that may be encountered with emerging VLSI/VHSIC technologies and describes a method that, if implemented, could minimize costs and adverse schedule impact to the user.

A hardware design, called the ME/ MRVQ, which combines the functions of motion estimation and mean/residual vector quantization (MRVQ) is proposed to improve the coding quality of MPEG and it is shown that the rate-distortion performance is uniformly improved.

Abstract : Many of the major semiconductor manufacturers have published the results of their own in-house design evaluations of new electrostatic discharge (ESD) protection networks. Several major users have published test and evaluation results on the ESD protection networks used on a wide cross-section of popular device types available today. The present work was undertaken to expand that data base and to compare the failure mechanisms which occur in devices subjected to both the human body and the charged device ESD simulation tests. The conclusions of this report are similar to those other...

Application of this basic filter structure to provide high-speed solutions for other standard signal processing transforms such as the Discrete Fourier Transform, the Chirp Z Transform, and the Running Discrete Discrete Transform is presented.

This research project presents a solution based approach using VLSI Technology that could be a moderate solution approach when in communication allied areas there would be need for the digital form and its allied applications.

Technological considerations of direct wafer stepping are examined and the requirements of high volume V.L.S.I. production are identified. An advanced step-and-repeat alignment system is presented which fulfills, to a high degree, the criteria developed. Its high numerical aperture 10:1 reduction lens provides high resolution at high contrast level. A new designed illumination system supplies high exposure intensity at excellent uniformity. An automatic step-by-step alignment, focusing and leveling system compensates for irregular wafer topography and its changes during processing. By the capa...

This paper presents a formalism for describing the behavior of computational networks at the algorithmic level that establishes a direct correspondence between mathematical expressions defining a function and the networks which compute that function.

Implementation of a MOS VLSI back-projection processor is well advanced with working designs obtained for most processor subsystems and accommodates non-linearity in the geometrical relationship between an image and its projection.

An algorithm for performing area-time efficient division, on-line techniques for performing bit-serial calculations, and iterative algorithms for performing square root are described.

The purpose of this project is to find efficient algorithms for testing L SI/VLSI chips and LSI/VSLI-based systems to validate correct functional operations of digital systems according to their specifications.

This thesis investigates and resolves some of the most important implementation issues not encountered in traditional designs in highly parallel cellular architectures, and presents a case study of architectures for a family of information retrieval tasks.

This report examines the complexities in volume and maximum wire length of mapping circuits represented as undirected graphs to 3-D systems and develops a cost model to reflect the cost implementation in the third dimension and an optimization model on the number of layers to minimize the overall cost.

A comparison of the different implementation techniques is provided, as is the type of paradigm implemented (e.g., backpropagation, hopfield, bidirectional associative memories, etc.).

This paper focuses on the security evaluation method of VLSI design front-end based on formal verification theory, which is adopted in the security check of a space Application Specific Integrated Circuit (ASIC).

One of the most critical issues facing the semiconductor industry is process testing and evaluation, and final circuit electrical tests provide the most comprehensive information in terms of establishing circuit functionality and implementing the necessary process adjustments.

Two VLSI architectures are introduced for high speed recognition of general context-free languages based on the Cocke-Younger-Kasami algorithm and Earley's algorithm.

An analysis of the MacPitts silicon compiler is presented, with the emphasis on the interrelationshp between algorithmic syntax and resulting circuit structure.