Top Research Papers on VLSI Design PDF

VLSI is concerned with forming a pattern of interconnected switches and gates on the surface of a crystal of semiconductor that has made highly sophisticated control systems mass-producable and therefore cheap.

Very large scale integrated circuits are difficult to test once fabricated, due to the large number of internal circuit nodes that are not accessible as probe points, and the small number of primary inputs and outputs available to exercise and observe these internal nodes.

The vlsi 81 very large scale integration is universally compatible with any devices to read, and is available in the digital library an online access to it is set as public so you can download it instantly.

Dielectric films are an integral part of the integrated circuits. Key applications can be classified as, (i) dielectrics for growing semiconductor films e.g., silicon on insulator, (ii) layer of dielectric films which do not appear in the finished device e.g., dielectrics for diffusion and ion implantation masks, and (iii) permanent dielectric films which play a key role in the electrical operation of the circuit e.g., gate dielectric in a MOSFET. In this paper a review is presented of the dielectrics with main emphasis on the permanent dielectric films. Techniques for forming dielectric films...

Modified decoding algorithms for DS codes are proposed that provide error detection when the number of correctable bit errors is exceeded by one and combined error detection and correction capability of the modified decoder are provide.

During the period covered by the grant, two books and ten research papers were written under grant sponsorship, and nineteen of the researchpapers were written and published in conference proceeding.

The proposed approach approximates the circuit performances, such as gain and delay, by fitted models, and uses them as surrogates of the circuit simulator to predict and optimize the parametric yield with computation efficiency and to achieve off-line quality control.

An overview of LSI/VLSI systems that brings together all their engineering aspects with economical considerations such as production volume economy, yield economy, chip pricing, and custom design methodology. Offers clear, concise explanations of how to design LSI/VLSI chips and what advantages and disadvantages accompany their use. The well-illustrated text includes worked examples as well as extensive references for further study.

We present on the demonstration of a number of critical device technologies including record low power modulators, tunable filters, and integrated lasers, along with the world's largest silicon photonic circuit, integrated on a 300mm platform.

This report summarizes progress in the DARPA funded VLSI Systems Research Projects from December 1986 to March 1987.

This report describes work performed on the Restructurable VLSI program sponsored by the Information Processing Techniques Office of the Defense Advanced Research Projects Agency during the period 1 April through 30 September 1984.

An algorithm for performing area-time efficient division, on-line techniques for performing bit-serial calculations, and iterative algorithms for performing square root are described.

An analysis of the MacPitts silicon compiler is presented, with the emphasis on the interrelationshp between algorithmic syntax and resulting circuit structure.

The verification platform and method use perl to realize the processing of a result, realize the automatic iterative verification of unmatch points, respectively manage a source code of each module to be verified and Lib, and greatly reduce the consumption of a reading time.

This paper describes the design of a very large scale integration (VLSI) application specific integrated circuit (ASIC) for use in pattern recognition and resolved the long delay time of the multiplier by custom designing adder cells based on the Manchester carry chain.

This thesis proposes to reduce the complexity of the design problem and the design time by using a high-level language to specify only the behavioral aspects of a circuit.

This research has the potential to provide savings of time and effort to engineers designing new circuits or reverse-engineering older circuits for which no adequate specifications exist and will also help to close the design cycle.

Automatic and bench techniques are used to characterize the performance of several VLSI memory types over the full military voltage and temperature ranges.

VLSI System Planning addresses this problem by modeling the practices of an expert designer in providing guidance at the initial stage of the design process as to the most promising design alternatives and giving a preliminary indication of the estimated performance.

This paper proposes a method based on projecting the image into characteristic subspaces using appropriate orthogonal basis functions that will be useful in hierarchical processing and fit well into a Very Large Scale Integrated (VLSI) circuit design.

PAPs are used as the baseline for the discussion of signal processing engines and are about to do to the conventional signal processors what microprocessors and PAPs did to mainframes.

The IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) systems is published as a monthly journal under the co-sponsorship of the IEEE Circuits and Systems Society, the IEEE Computer Society, and the IEEE Solid-State Circuits Society.

The Circuits and Systems Society is an association of IEEE members with professional interest in the field of circuits and systems theory and member copies of Transactions/Journals are for personal use only.

The IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS is published as a monthly journal under the co-sponsorship of the IEEE Circuits and Systems Society, the IEEE Computer Society, and the IEEE Solid-State Circuits Society. All members of the IEEE are eligible for membership in all three societies upon payment of membership fee. Current society membership fees are: Circuits and Systems Society-$22, Computer Society $60, and Solid-State Circuits-$22. For information on joining, visit the IEEE website at https://www.ieee.org/membership/join/index.html ?WT.mc id=hc join or write t...

This paper surveys several common computer networking approaches and presents a novel concept, the Gatlinburg Rings, which is shown to be attractive for large networks.

A practical algorithm for fault simulation which simultaneously determines all detectable S-A faults for every gate in the circuit tree C, which requires only the evaluation of a circuit FS(C) which has equal to or less than 3(d+1), when d is the depth of C.

The report describes the improvement in fault tolerance obtained as a result of implementing these EDAC schemes and the associated penalties in circuit area.

A synthesis algorithm finds a cascade of Toffoli and Fredkin gates with no backtracking and minimal look-ahead, and applies transformations that reduce the size of the circuit through template matching.

A family of "smart sensors" based on a micro - signal processor technique capable of identifying, detecting, and/or classifying particular target signatures in real - time with a high degree of reliability and flexibility while meeting system constraints of low cost, small size, and very low power dissipation is described.

This paper shows how one such system, a very high performance digital filter, is implemented using current technology.

This work is directed at obtaining special purpose structures for DSP tasks that are well suited for VLSI implementation.

This project is to establish, within a university research environment, a facility for the rapid execution of mask generation, wafer fabrication, and functional testing of user- generated custom I.C. designs.

A description is given of the various phases involved in reliability prediction model development, such as; literature collection/review, investigation of failure modes, failure rate data collection, statistical analysis methodologies, model factors quantification, and model validation.

A high—performance, cost—effective silicon—on—insulator (SOI) technology would have important near—term applications in radiation—hardened electronics and longer term applications in submicrometer VLSI. The advantages of SOI over bulk Si technology for these applications will be outlined, and CMOS, CJFET, andbipolar device structures being developed for SOI will be discussed. The current status and future prospects of the two most promising SOI technologies —— beam recrystallization and high—dose oxygen implantation —— will be reviewed, with emphasis on such issues critical to commercializatio...

This research presents an evolutionary computation algorithm for defect detection based on defective current and voltage considered based on various sizes and location of resistors, frequencies or voltage supply magnitudes using Genetic Algorithm.

A synthesis algorithm finds a cascade of Toffoli and Fredkin gates with no backtracking and minimal look-ahead, and applies transformations that reduce the size of the circuit through template matching.

An overview on architectures for VLSI implementations of video compression schemes as specified by standardization committees of the ITU and ISO, focussing on programmable architectures on heterogeneous and heterogeneous processor architectures is presented.

This paper will discuss one of the more advanced automated systems available, the TRE 800 SLR, and its engineering evaluation in the fabrication of VLSI circuits and emphasis will be placed on overlay accuracy including field-by-field registration, matching of steppers and mixing with other aligners.

This thesis is an introduction to the use of computer-aided design tools for the design of very large scale integrated circuits (VLSI) and a tutorial is given which illustrates their use in the computing environment at the Naval Postgraduate School.

The generalized Design Procedure for CAD circuit design is discussed; the connnercial CADs offered by CALMA and the Caesar System, supported by the Berkeley design tools are illustrated.

This paper proposes a new design of 2T AND gate and performance comparison of proposed gate with existing 2T GDI technique is presented to prove the superiority of proposed design over existing 2T gate design.

This research builds logic design and layout for basic logical gates, such as NOT, AND and SOP ( Sum of Product ).

This paper presents a comparative study of Field Programmable Gate Array implementation of standard multipliers using Verilog HDL, finding significant reduction in FPGA resources, delay, and power can be achieved using Reduced Wallace multipliers with Koggestone adder instead of standard parallel multipliers.

The process of employing the MacPitts silicon compiler to design an 8-bit pipelined digital multiplier is presented, and the resulting design is evaluated.

Abstract : The test methods of MIL-STD-883 were reviewed to assess their appropriateness in view of the new package styles and materials being used for BLSI/VHSIC devices. Experiments were performed to judge the effectiveness of existing tests. Changes to existing tests are proposed where deemed necessary and new tests are developed where no existing method adequately assess new technology devices. Proposed changes and/or new package tests evaluate: solderability of leads; pin grid lead pull strength; leadless chip carrier bond strength; die attach bond analysis; characteristic impedance, capa...

A new approach is described for the automatic detection of defects in VLSI circuit patterns such as photomasks and wafers based on morphological feature extraction using templates that represent a set of local pixel configurations within a specified window.

Criteria and procedures that provide assurance as to a manufacturer's ability to provide functionally reproducible and reliable devices are desirable prior to user commitment to the design of a custom device. Additions and modifications to current practices are necessary when procurement of small batches of high-density, custom microelectronic devices are anticipated. This paper analyzes the problems that may be encountered with emerging VLSI/VHSIC technologies and describes a method that, if implemented, could minimize costs and adverse schedule impact to the user.

A hardware design, called the ME/ MRVQ, which combines the functions of motion estimation and mean/residual vector quantization (MRVQ) is proposed to improve the coding quality of MPEG and it is shown that the rate-distortion performance is uniformly improved.

Abstract : Many of the major semiconductor manufacturers have published the results of their own in-house design evaluations of new electrostatic discharge (ESD) protection networks. Several major users have published test and evaluation results on the ESD protection networks used on a wide cross-section of popular device types available today. The present work was undertaken to expand that data base and to compare the failure mechanisms which occur in devices subjected to both the human body and the charged device ESD simulation tests. The conclusions of this report are similar to those other...

Application of this basic filter structure to provide high-speed solutions for other standard signal processing transforms such as the Discrete Fourier Transform, the Chirp Z Transform, and the Running Discrete Discrete Transform is presented.