GALS Networks on Chip: A New Solution for Asynchronous Delay-Insensitive Links
Published 1 January 2006
Giuseppe Campobello, Marco Castano, C. Ciofi, D. Mangano
Citations30
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TL;DR
The solution is based on the Berger coding scheme and allows to obtain a very low wire overhead and shows that a 64-bit link can be built paying a wire overhead of 10% and 30 equivalent two-input gates per wire.
Abstract
In this paper a cost effective solution for asynchronous delay-insensitive on-chip communication is proposed. Our solution is based on the Berger coding scheme and allows to obtain a very low wire overhead. For instance, the results of our evaluation show that a 64-bit link can be built paying a wire overhead of 10% and 30 equivalent two-input gates per wire. As a general rule, when the number of bits to be transmitted increases, the wire overhead decreases and the gate overhead remains almost the same
Keywords
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