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Design and implementation of the POWER5/spl trade/ microprocessor

Published 28 September 2004
J. Clabes, J. Friedrich, M. Sweet, J. DiLullo, Sam Chu, D. Plass
Citations23

TL;DR

POWER5/sup TM/ is the next generation of IBM's POWER microprocessors, sets a new standard of server performance by incorporating simultaneous multithreading (SMT), an enhanced distributed switch and memory subsystem supporting 164w SMP, and extensive RAS support.

Abstract

POWER5 offers /spl sim/4/spl times/ performance over the previous design by incorporating simultaneous multithreading, a latency-optimized memory subsystem, extensive reliability, availability and serviceability (RAS), and power management support. The 276M-transistor processor is implemented in a 0.13 /spl mu/m, 8M silicon-on-insulator technology and operates above 1.5 GHz.

Keywords

Computer ScienceEngineering