A Placement Algorithm for Polycell LSI and its Evaluation
Design Automation ConferencePublished 1 January 1982
Takashi Kambe, T. Chiba, Seiji Kimura, Tsuneo Inufushi, Noboru Okuda, Ikuo Nishioka
Citations14
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Abstract
An automatic placement algorithm for standard cell and polycell LSI is described, which is constructed on the basis of heuristics for a set of interrelated placement subproblems. The algorithm is incorporated into a hierarchical layout system intended not only for standard cell and polycell LSI but for general cell LSI, by which standard cell and polycell LSI have begun to be laid out in practice. A part of implementation results are also shown to reveal how high the layout performance of the placement program.
Keywords
Engineering
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