Feature - Xpipes : a network-on-chip architecture for gigascale systems-on-chip
IEEE Circuits and Systems MagazinePublished 1 January 2004
Davide Bertozzi, Luca Benini
Citations416
SJR quartileQ1
SJR score1.34
SNIP2.93
Generate an AI Snapshot to get a quick, structured summary of this paper.
Study Snapshot
ObjectiveStudy objective
MethodsResearch methodology
PopulationPopulation studied
Sample sizeSample sizes
OutcomesStudy outcomes here
ResultsStudy results comes here
LimitationsResearch study limitations comes here
A concise AI-generated summary of the paper will appear here once you click Generate AI Snapshot.
TL;DR
An advanced NoC architecture, called Xpipes, targeting high performance and reliable communication for on-chip multi-processors is introduced, which consists of a library of soft macros that are design-time composable and tunable so that domain-specific heterogeneous architectures can be instantiated and synthesized.
Abstract
The growing complexity of embedded multiprocessor architectures for digital media processing will soon require highly scalable communication infrastructures. Packet switched networks-on-chip (NoC) have been proposed to support the trend for systems-on-chip integration. In this paper, an advanced NoC architecture, called Xpipes, targeting high performance and reliable communication for on-chip multi-processors is introduced. It consists of a library of soft macros (switches, network interfaces and links) that are design-time composable and tunable so that domain-specific heterogeneous architectures can be instantiated and synthesized. Links can be pipelined with a flexible number of stages to decouple link throughput from its length and to get arbitrary topologies. Moreover, a tool called XpipesCompiler, which automatically instantiates a customized NoC from the library of soft network components, is used in this paper to test the Xpipes-based synthesis flow for domain-specific communication architectures.
Keywords
Computer ScienceEngineering
ComputerNetworks on chips: a new SoC paradigm
3,705 Citations2002Luca Benini, Giovanni De Micheli
Focusing on using probabilistic metrics such as average values or variance to quantify design objectives such as performance and power will lead to a major change in SoC design methodologies.
Route packets, net wires
3,209 Citations2001William J. Dally, Brian Towles
The concept of on-chip networks is introduced, a simple network is sketched, and some challenges in the architecture and design of these networks are discussed.
Parallel Computer Architecture: A Hardware/Software Approach
1,378 Citations1998David Culler, Anoop Gupta +1 more
This book explains the forces behind this convergence of shared-memory, message-passing, data parallel, and data-driven computing architectures and provides comprehensive discussions of parallel programming for high performance and of workload-driven evaluation, based on understanding hardware-software interactions.
ACM Computing SurveysReconfigurable computing
1,231 Citations2002Katherine Compton, Scott Hauck
The hardware aspects of reconfigurable computing machines, from single chip architectures to multi-chip systems, including internal structures and external coupling are explored, and the software that targets these machines is focused on.
A network on chip architecture and design methodology
1,195 Citations2003Shashi Kumar, Axel Jantsch +6 more
A packet switched platform for single chip systems which scales well to an arbitrary number of processor like resources which is the onchip communication infrastructure comprising the physical layer, the data link layer and the network layer of the OSI protocol stack.
A generic architecture for on-chip packet-switched interconnections
831 Citations2000Pierre Guerrier, Alain Greiner
This paper presents an architectural study of a scalable system-level interconnection template, and discusses the necessity and the ways to provide high-level services on top of the bare network packet protocol, such as dataflow and address-space communication services.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and SystemsTheory of latency-insensitive design
432 Citations2001Luca P. Carloni, Kenneth L. McMillan +1 more
The theory of latency-insensitive design is presented as the foundation of a new correct-by-construction methodology to design complex systems by assembling intellectual property components to design large digital integrated circuits by using deep submicrometer technologies.
Design, Automation, and Test in EuropeTrade Offs in the Design of a Router with Both Guaranteed and Best-Effort Services for Networks on Chip
379 Citations2003E. Rijpkema, Kees Goossens +5 more
The Journal of VLSI Signal Processing Systems for Signal Image and Video TechnologyReconfigurable Computing for Digital Signal Processing: A Survey
323 Citations2001Russell Tessier, Wayne Burleson
It is shown that while contemporary reconfigurable computing can be applied to a variety of DSP applications including video, audio, speech, and control, much work remains to realize its full potential.
Proceedings Design, Automation and Test in Europe Conference and Exhibition 2000 (Cat. No. PR00537)A generic architecture for on-chip packet-switched interconnections
319 Citations2002Pièrre Guerrier, Alain Greiner
High-Performance Communication Networks
316 Citations1999Jean Walrand, Pravin Varaiya
This in-depth presentation of emerging technologies used to build high speed, high performance communication networks explains how the converging telephone, data, and CATV technologies are combined into high performance networks and how to plan, manage, and control these networks.
IEEE Transactions on Very Large Scale Integration (VLSI) SystemsLow-swing on-chip signaling techniques: effectiveness and robustness
293 Citations2000H. Zhang, Varghese George +1 more
This paper reviews a number of low-swing on-chip interconnect schemes and presents a thorough analysis of their effectiveness and limitations, especially on energy efficiency and signal integrity, and several new interface circuits presenting even more energy savings and better reliability are proposed.
Computer2001 technology roadmap for semiconductors
256 Citations2002AJ Allan, D. Edenfeld +4 more
Representatives of the International Technology Working Groups for Design and Test showcase some of the contributions from 839 international experts seeking to address the difficult and exciting challenges facing the design and test communities and the semiconductor industry as a whole.
Design, Automation, and Test in Europe×pipesCompiler: A Tool for Instantiating Application Specific Networks on Chip
208 Citations2004Antoine Jalabert, Srinivasan Murali +2 more
Xpipes: A latency insensitive parameterized network-on-chip architecture for multi-processor SoCs
185 Citations2012Matteo Dall'Osso, Gianluca Biccari +3 more
This paper proposes xpipes, a scalable and high-performance NoC architecture for multi-processor SoCs, consisting of soft macros that can be turned into instance-specific network components at instantiation time, to support both homogeneous and heterogeneous architectures.
2003 Design, Automation and Test in Europe Conference and ExhibitionTrade offs in the design of a router with both guaranteed and best-effort services for networks on chip
176 Citations2003E. Rijpkema, Kees Goossens +5 more
This paper combines the GT and BE router architectures in an efficient implementation by sharing resources, and shows the trade offs between hardware complexity and efficiency of the combined router, and the motivation of the choices.
Proceedings Design, Automation and Test in Europe Conference and Exhibition×pipesCompiler: a tool for instantiating application specific networks on chip
161 Citations2004Antoine Jalabert, Srinivasan Murali +2 more
Micronetwork-based integration for SOCs
153 Citations2001Drew Wingard
The concept of using an on-chip network as the fundamental communication architecture for a complex SOC design is described, some of the salient features of a MicroNetwork are described, and an automated development environment is introduced that makes MicroNetwork-based design productive.
Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIEMapping of MPEG-4 decoding on a flexible architecture platform
140 Citations2001Erik B. van der Tol, E.G.T. Jaspers
The mapping study of the MPEG-4 decoder proves the flexibility and extensibility of the media-processing platform and enables an effective HW/SW co-design yielding a high performance density.
IEEE Journal of Solid-State CircuitsA 1-V heterogeneous reconfigurable DSP IC for wireless baseband digital signal processing
104 Citations2000H. Zhang, V. Prabhu +5 more
A heterogeneous reconfigurable platform enables the flexible implementation of baseband wireless functions at energy levels between 10 and 100 MOPS/mW, six times higher than traditional digital signal processors.
Guaranteeing the Quality of Services in Networks on Chip
92 Citations2003Kees Goossens, J. Dielissen +6 more
The AETHEREAL NOC is an example of this approach, and forms the basis of a QOS-based design style, as advocated in this chapter.
VLSI architecture: past, present, and future
78 Citations1999William J. Dally, S. Lacy
The architecture of a VLSI multicomputer constructed from c.
Xpipes: a latency insensitive parameterized network-on-chip architecture for multiprocessor SoCs
76 Citations2004M. Dall'Osso, G. Biccari +3 more
Xpipes is proposed, a scalable and high-performance NoC architecture for multiprocessor SoCs, consisting of soft macros that can be turned into instance-specific network components at instantiation time, allowing the NoC to support both homogeneous and heterogeneous architectures.
An 800MHz star-connected on-chip network for application to systems on a chip
76 Citations2003Se-Joong Lee, Seong-Jun Song +5 more
A 10.8/spl times/6.0mm/sup 2/ prototype chip is implemented with a star-connected on-chip network, supporting plesiochronous communication without global synchronization.
Interconnect IP node for future system-on-chip designs
74 Citations2003Ilkka Saastamoinen, David A. Sigüenza-Tortosa +1 more
An interconnect IP (intellectual Property) node architecture for flexible on-chip communication is introduced, targeted for communication in future gigatransistor SoC (System-on-Chip) designs.
Networks on silicon: blessing or nightmare?
71 Citations2003P. Wielage, Kees Goossens
This work introduces networks on silicon (NoS), that route packets over shared (semi)-global wires, and believes busses still have a role to play in the future of NoS.
2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)Ambient intelligence, the next paradigm for consumer electronics: how will it affect silicon?
47 Citations2003F. Boekhorst
Some of the technologies required for Ambient Intelligence are covered, with a focus on IC consequences, and ongoing work in three fields is described: ubiquitous radio, intuitive user/system interfaces and three-dimensional visual displays.
Methodologies and tools for pipelined on-chip interconnect
44 Citations2003Louis K. Scheffer
This work looks at some ways that practical difficulties of pipeline the global interconnect, enabling the whole chip to run at the speed of local operations, could be overcome.
IEEE Journal of Solid-State CircuitsA single-chip MPEG-2 codec based on customizable media embedded processor
27 Citations2003Shunichi Ishiwata, Tomoo Yamakage +14 more
A single-chip MPEG-2 MP@ML codec, integrating 3.8M gates on a 72-mm/sup 2/ die, is described, which employs a heterogeneous multiprocessor architecture in which six microprocessors with the same instruction set but different customization execute specific tasks such as video and audio concurrently.
Kluwer Academic Publishers eBooksWill Networks on Chip Close the Productivity Gap?
26 Citations2005Axel Jantsch, Hannu Tenhunen
It is argued that the emerging Network-on-Chip (NoC) paradigm promises to address these trends and challenges and has all prerequisites to provide the arbitrary composability and the linear effort properties.
Wave pipelining for application-specific networks-on-chips
15 Citations2002Jiang Xu, Wayne Wolf
This paper presents methods for optimizing application-specific networks-on-chips (NoCs) and shows how designers can tune their network to the requirements of the application by choosing a design point along area/performance or area/energy curves.
2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)A 0.8 W HDTV video processor with simultaneous decoding of two MPEG2 MP@HL streams and capable of 30 frames/s reverse playback
15 Citations2002H. Yamauchi, Y. Matsushita +8 more
SoC BUS : The solution of high communication bandwidth on chip and short TTM
13 Citations2002Dake Liu, Daniel Wiklund +3 more
A novel concept, PCC: Packet Connected Circuit, which reaches fixed and low transfer latency based on high bandwidth supporting multiple simultaneous data transfer and a SoC system designer’s methodology is proposed so that a short TTM SoC design is possible.
Energy-Reliability trade-Off for NoCs
9 Citations2003Davide Bertozzi, Luca Benini +1 more
In this chapter, the theoretical framework for energy and realiability analysis is introduced and several error control and recovery strategies are investigated in a realistic SoC setting.