Efficient circuit partitioning to extend cycle simulation beyond synchronous circuits

A novel partitioning algorithm is presented that partitions a non-cycle-simulatable circuit containing circuit features like combinational paths, multiple clock domains, generated clocks, asynchronous resets, and transparent latches into simulation that can be cycle simulated.

Abstract

Cycle simulation techniques, such as levelized compiled code, can ordinarily be applied only to synchronous designs. They usually cannot be applied to designs containing circuit features like combinational paths, multiple clock domains, generated clocks, asynchronous resets, and transparent latches. This paper presents a novel partitioning algorithm that partitions a non-cycle-simulatable circuit containing these features into simulation that can be cycle simulated. Cycle simulation techniques can be applied to the individual sub-circuits, and the whole collection of sub-circuits can be simulated together using conventional co-simulation techniques. Empirical results demonstrate that this approach brings the benefits of cycle simulation to circuits that were previously impossible to cycle simulate. The partitioning algorithm requires time and space linear in the size of the circuit, and in practice is very fast. We also discuss how the key ideas presented here can be applied to accelerate HDL simulation.