Binary LNS-based naive Bayes inference engine for spam control: noise analysis and FPGA implementation

IET Computers & Digital TechniquesPublished 9 January 2008

Muhammad Nadzir Marsono, M. Watheq El‐Kharashi, Fayez Gebali

DOI10.1049/iet-cdt:20050180

Source URL

Citations27

SJR quartileQ3

SJR score0.22

SNIP0.53

TL;DR

A hardware architecture for naive Bayes inference engine to classify e-mail contents for spam control and a non-iterative binary LNS recoding hardware architecture that uses look-up table approach are proposed.

Abstract

A hardware architecture for naïve Bayes inference engine to classify e-mail contents for spam control is proposed. The inference engine utilises the logarithmic number system (LNS) to simplify naïve Bayes computations. For high throughput LNS recoding, a non-iterative binary LNS recoding hardware architecture that uses look-up table approach is proposed. A noise model for the inference engine was developed and the noise bounds were analysed to determine the inference accuracy. The inference engine design is synthesised targeting the Altera Stratix field programmable gate array (FPGA) device. From the synthesis results, the binary LNS naïve Bayes inference engine was found to have the capability to classify more than 117 million features per second, given a stream of a priori and likelihood probabilities as input with small computation noise. The synthesised inference engine was functionally verified against a MATLAB implementation.

Keywords

Computer Science

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