System-level performance evaluation of three-dimensional integrated circuits
IEEE Transactions on Very Large Scale Integration (VLSI) SystemsPublished 1 December 2000Open access
Arif Rahman, R. Reif
Citations199
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TL;DR
The wire (interconnect)-length distribution of 3-D integrated circuits (ICs) is derived using Rent's rule and following the methodology used to estimate two-dimensional (2-D) (wire-length distribution).
Abstract
Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2001.
Keywords
Computer ScienceEngineering
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