Performance-driven soft-macro clustering and placement by preserving HDL design hierarchy
Published 1 April 1998
Hsiao-Pin Su, Allen C.-H. Wu, Youn-Long Lin
Citations23
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TL;DR
A performance-driven soft-macro clustering and placement method which preserves HDL design hierarchy to guide the soft- Macro placement process and a complete chip design methodology is presented by integrating the proposed method and a set of commercial EDA tools.
Abstract
In this paper, we present a performance-driven soft-macro clustering and placement method which preserves HDL design hierarchy to guide the soft-macro placement process. We also present a complete chip design methodology by integrating the proposed method and a set of commercial EDA tools. Experiments on three industrial designs ranging from 75K to 230K gates demonstrate that the proposed soft-macro clustering and placement method improves critical-path delay on an average of 24%.
Keywords
Computer ScienceEngineering
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