A hybrid floating-point logarithmic number system processor
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TL;DR
A hybrid system which does not require exponent alignment during addition, supports high-speed addition and multiplication, has an efficient accumulator structure, and admits a simple VLSI realization is proposed.
Abstract
The attributes of the traditional floating-point processor and the logarithmic number system are combined. The result is a hybrid system which offers some advantages over the familiar floating-point system. The new system, called the (FU)^{2} , does not require exponent alignment during addition, supports high-speed addition and multiplication, has an efficient accumulator structure, and admits a simple VLSI realization.