Locality-conscious workload assignment for array-based computations in MPSOC architectures

A compiler-driven data locality optimization strategy in the context of embedded MPSOCs is proposed and it is shown that the global scheme brings significant power/performance benefits over the conventional loop based scheme.

Abstract

While the past research discussed several advantages of multipro-cessor-system-on-a-chip (MPSOC) architectures from both area uti-lization and design verification perspectives over complex single core based systems, compilation issues for these architectures have relatively received less attention. Programming MPSOCs can be challenging as several potentially conflicting issues such as data locality, parallelism and load balance across processors should be considered simultaneously. Most of the compilation techniques discussed in the literature for parallel architectures (not necessar-ily for MPSOCs) are loop based, i.e., they consider each loop nest in isolation. However, one key problem associated with such loop based techniques is that they fail to capture the interactions be-tween the different loop nests in the application. This paper takes a more global approach to the problem and proposes a compiler-driven data locality optimization strategy in the context of embed-ded MPSOCs. An important characteristic of the proposed ap-proach is that, in deciding the workloads of the processors (i.e., in parallelizing the application) it considers all the loop nests in the application simultaneously. Our experimental evaluation with eight embedded applications shows that the global scheme brings signif-icant power/performance benefits over the conventional loop based scheme.