Automation of IC layout with analog constraints
IEEE Transactions on Computer-Aided Design of Integrated Circuits and SystemsPublished 1 January 1996Open access
E. Malavasi, Edoardo Charbon, Eric Felt, Alberto Sangiovanni‐Vincentelli
Citations184
SJR quartileQ1
SJR score0.72
SNIP1.34
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TL;DR
A methodology for the automatic synthesis of full-custom IC layout with analog constraints is presented, guaranteeing that all performance constraints are met when feasible, or otherwise, infeasibility is detected as soon as possible, thus providing a robust and efficient design environment.
Abstract
A methodology for the automatic synthesis of full-custom IC layout with analog constraints is presented. The methodology guarantees that all performance constraints are met when feasible, or otherwise, infeasibility is detected as soon as possible, thus providing a robust and efficient design environment. In the proposed approach, performance specifications are translated into lower-level bounds on parasitics or geometric parameters, using sensitivity analysis. Bounds can be used by a set of specialized layout tools performing stack generation, placement, routing, and compaction. For each tool, a detailed description is provided of its functionality, of the way constraints are mapped and enforced, and of its impact on the design flow. Examples drawn from industrial applications are reported to illustrate the effectiveness of the approach.
Keywords
Computer ScienceEngineering
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