4GHz+ low-latency fixed-point and binary floating-point execution units for the POWER6 processor
Published 1 January 2006
Brian Curran, B.D. McCredie, L. Sigal, E. Schwarz, Bruce Fleischer, Yiu-Hing Chan
Citations18
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TL;DR
A 1-pipe stage, low-latency, 13 FO4, 64b fixed-point execution unit, implemented in a 65nm SOI CMOS process, allows back-to-back execution of data dependent adds, subtracts, compares, shifts, rotates, and logical operations.
Abstract
A 1-pipe stage, low-latency, 13 FO4, 64b fixed-point execution unit, implemented in a 65nm SOI CMOS process, allows back-to-back execution of data dependent adds, subtracts, compares, shifts, rotates, and logical operations. A 7-pipe stage, 91 FO4, double-precision floating-point unit allows forwarding of dependent results after 6 cycles in most cases
Keywords
Computer Science
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