DCG: deterministic clock-gating for low-power microprocessor design

A deterministic clock-gating (DCG) technique which effectively reduces clock power in high-performance processors by applying DCG to execution units, pipeline latches, D-cache wordline decoders, and result bus drivers.

Abstract

With the scaling of technology and the need for higher performance and more functionality, power dissipation is becoming a major bottleneck for microprocessor designs. Because clock power can be significant in high-performance processors, we propose a deterministic clock-gating (DCG) technique which effectively reduces clock power. DCG is based on the key observation that for many of the pipelined stages of a modern processor, the circuit block usage in the near future is known a few cycles ahead of time. Our experiments show an average of 19.9% reduction in processor power with virtually no performance loss for an eight-issue, out-of-order superscalar by applying DCG to execution units, pipeline latches, D-cache wordline decoders, and result bus drivers.