Simplified clock voltage doubler
Electronics LettersPublished 28 October 1999
S. Basu, Gábor C. Temes
Citations7
SJR quartileQ3
SJR score0.27
SNIP0.44
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Abstract
A simple clock voltage doubler, based on the Nakagome charge pump, is described. It prevents the latch-up of the output switch without requiring an extra charge-pump voltage doubler.
Keywords
EngineeringChemical Engineering
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