High-bandwidth data memory systems for superscalar processors
ACM SIGPLAN NoticesPublished 1 April 1991Open access
Gurindar S. Sohi, Manoj Franklin
Citations6
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Abstract
This paper considers the design of a data memory hierarchy, with a level 1 (L1) data cache at the top, to support the data bandwidth demands of a future-generation superscalar processor capable of issuing about ten instructions per clock cycle. It introduces the notion of cache
Keywords
Computer Science
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