Integrated hardware/software design of a high performance network interface

This thesis describes the design and implementation of a high performance network interface chip called the APIC (ATM Port Interconnect Controller) and describes architectural enhancements to operating system (OS) software that are necessary to exploit some of the novel features that have been integrated into this chip.

Abstract

One of the ways in which the APIC addresses the memory bottleneck alluded to above is to function in a desk-area environment where different memories can be used to spread the load. The idea here is to dedicate one APIC chip and one memory bank to each high-bandwidth device in the system, thereby shedding the load from a host system's main memory. Several such APIC-memory device combinations can be daisy chained to form a desk-area network with high bandwidth and low latency characteristics.