Post-placement residual-overlap removal with minimal movement
Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078)Published 20 January 2003
S. Nag, K. Chaudhary
Citations5
Generate an AI Snapshot to get a quick, structured summary of this paper.
Study Snapshot
ObjectiveStudy objective
MethodsResearch methodology
PopulationPopulation studied
Sample sizeSample sizes
OutcomesStudy outcomes here
ResultsStudy results comes here
LimitationsResearch study limitations comes here
A concise AI-generated summary of the paper will appear here once you click Generate AI Snapshot.
Abstract
In this paper we present a novel approach for removing residual overlaps among blocks. We start out by representing the placement in the sequence pair form and describe transformations to the sequence pair to make the placement feasible. This is followed by a distance-based slack allocation to generate a new placement with no overlaps, while being as close to the original placement as possible. Our results demonstrate the efficacy of our approach in transforming layouts with overlaps to overlap-free layouts with minimal object movement.
Keywords
Computer ScienceEngineering
23rd ACM/IEEE Design Automation ConferenceA New Algorithm for Floorplan Design
369 Citations1986Martin D. F. Wong, C.L. Liu
IEEE Journal of Solid-State CircuitsKOAN/ANAGRAM II: new tools for device-level analog placement and routing
329 Citations1991John M. Cohn, David J. Garrod +2 more
KOAN and ANAGRAM II differ from previous approaches by using general algorithmic techniques to find critical device-level layout optimizations rather than relying on a large library of fixed-topology module generators.
Proceedings of IEEE International Conference on Computer Aided Design (ICCAD)Rectangle-packing-based module placement
254 Citations2002Hideyuki Murata, Kunihiro Fujiyoshi +2 more
This paper proposes a solution space where each packing is represented by a pair of module name sequences and, by simulated annealing, hundreds of modules could be successfully packed as demonstrated.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and SystemsSimultaneous Floor Planning and Global Routing for Hierarchical Building-Block Layout
135 Citations1987Wei-Ming Dai, E.S. Kuh
The experimental results on examples with a large number of irregular blocks show that the new methodology out-performs other well-known deterministic algorithms, and gives results that are comparable to random-based algorithms but with a computing time an order of magnitude less.
IEEE Transactions on Circuits and Systems II Analog and Digital Signal ProcessingRITUAL: a performance driven placement algorithm
65 Citations1992A. Srinivasan, K. Chaudhary +1 more
An algorithm for obtaining a placement of large scale cell-based ICs subject to performance constraints, formulated as a constrained programming problem and solved in two phases: continuous and discrete.
[1992] Proceedings 29th ACM/IEEE Design Automation ConferenceIterative and adaptive slack allocation for performance-driven layout and FPGA routing
53 Citations2003J. Frankle
A generalization of a procedure of H. Youssef et al. (1990) that transforms initial connection delays into upper limits on delay suitable for performance-driven layout is given.
Timing constraints for correct performance
52 Citations2002Habib Youssef, Eugene Shragowitz
Novel methodology and algorithms for the derivation of timing constraints on all the interconnects were developed and applied to solving layout related timing problems and zero slack is achieved.
Floorplanning by topological constraint reduction
12 Citations2002G. Vijayan, Ren‐Song Tsay
The floorplanning approach described is targeted for multilayer sea-of-cells based designs and it is assumed that no channel separations are required between the blocks, so the approach can be generalized to incorporateChannel separations.
