SoC Leakage Power Reduction Algorithm by Input Vector Control

Published 1 January 2005

Xiaotao Chang, Dongrui Fan, Yinhe Han, Zhimin Zhang

DOI10.1109/issoc.2005.1595651

Citations8

TL;DR

Experimental results on large combinational circuits of ISCAS85 benchmark and a real general-purpose SoC show this algorithm can accelerate calculation over three times with acceptable accuracy (error about 0.14%).

Abstract

Input vector control is an effective method to reduce leakage power when a circuit enters sleep mode. It seeks to find a vector that minimizes leakage power to be statically applied to the primary inputs of a circuit. This paper presents a fast algorithm to search the input vector which can lead to the minimal leakage power. In order to accelerate the evaluation procedure, the circuit under simulation is reduced by circuit partition based on the signal probability model first. Then, a searching algorithm based on sub-circuit is used to find the target input vector. Experimental results on large combinational circuits of ISCAS85 benchmark and a real general-purpose SoC show this algorithm can accelerate calculation over three times with acceptable accuracy (error about 0.14%).

Keywords

Computer ScienceEngineering

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