FPGA implementation of an adaptable-size neural network

Lecture notes in computer sciencePublished 1 January 1996Open access

Andrés Pérez-Uribe, Eduardo García Sánchez

Citations39

TL;DR

This paper describes an FPGA implementation of the FAST (Flexible Adaptable-Size Topology) architecture, a neural network that dynamically changes its size, and applies this dynamic-structure FAST neural network to an image segmentation and recognition problem.

Abstract

Artificial neural networks achieve fast parallel processing via massively parallel non-linear computational elements. Most neural network models base their ability to adapt to problems on changing the strength of the interconnections between computational elements according to a given learning algorithm. However, constrained interconnection structures may limit such ability. Field programmable hardware devices allow the implementation of neural networks with in-circuit structure adaptation. This paper describes an FPGA implementation of the FAST (Flexible Adaptable-Size Topology) architecture, a neural network that dynamically changes its size. Since initial experiments indicated a good performance on pattern clustering tasks, we have applied our dynamic-structure FAST neural network to an image segmentation and recognition problem.

Keywords

Computer ScienceEngineering

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