A true single-phase-clock dynamic CMOS circuit technique
IEEE Journal of Solid-State CircuitsPublished 1 October 1987
Y. Ji-Ren, Ingrid Karlsson, C. Svensson
Citations231
SJR quartileQ1
SJR score3.36
SNIP3.12
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TL;DR
The authors describe two dynamic circuit techniques, using only a single-phase clock which is never inverted, which has the advantages of simple clock distribution, small area for clock lines reduced clock skew problems, and high speed.
Abstract
The authors describe two dynamic circuit techniques, using only a single-phase clock which is never inverted. This class of circuits has the advantages of simple clock distribution, small area for clock lines reduced clock skew problems, and high speed. Several examples are demonstrated.
Keywords
Engineering
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