Phase-Change Technology and the Future of Main Memory
IEEE MicroPublished 1 January 2010
Benjamin C. Lee, Ping Zhou, Jun Yang, Youtao Zhang, Bo Zhao, Engin İpek
Citations404
SJR quartileQ1
SJR score0.94
SNIP1.40
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TL;DR
This article discusses how to mitigate limitations through buffer sizing, row caching, write reduction, and wear leveling, to make PCM a viable dream alternative for scalable main memories.
Abstract
Phase-change may enable continued scaling of main memories, but PCM has higher access latencies, incurs higher power costs, and wears out more quickly than DRAM. This article discusses how to mitigate these limitations through buffer sizing, row caching, write reduction, and wear leveling, to make PCM a viable dream alternative for scalable main memories.
Keywords
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