A VLSI architecture design of an edge based fast intra prediction mode decision algorithm for h.264/avc

Published 11 March 2007

Shen Li, Xianghui Wei, Takeshi Ikenaga, Satoshi Goto

Citations18

TL;DR

A novel VLSI design is presented of an edge based fast intra MD algorithm which can constantly reduce about 66% of the RD related computation with a negligible quality loss and is expected to be utilized as a favorable accelerator hardware module in a real-time HDTV (1920-1088p) H.264 encoder or MPEG2-H.264 transcoder.

Abstract

The intra-frame coding in H.264/AVC has made significant contribution to the enhancement of coding efficiency. However it brings about a heavy computation burden in the rate distortion based (RD) mode decision (MD) process. Although the real-time encoding of 1280-720p signals is realized in recent works with existing algorithms, for higher resolution e.g. 1920-1088p some hardware-oriented fast algorithms are necessary. Yet so far few of the many proposed fast MD algorithms have seen successful hardware implementation. This paper presents a novel VLSI design (15.8k [email protected], with TSMC CMOS 0.18μm technology) of an edge based fast intra MD algorithm which can constantly reduce about 66% of the RD related computation with a negligible quality loss. It is expected to be utilized as a favorable accelerator hardware module in a real-time HDTV (1920-1088p) H.264 encoder or MPEG2-H.264 transcoder.

Keywords

Computer Science

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