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Design of the Power6 Microprocessor

Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits ConferencePublished 1 February 2007
Joshua Friedrich, B.D. McCredie, N. James, Bill Huott, Brian Curran, Eric Fluhr
Citations114
SJR score4.00
SNIP3.42

TL;DR

The POWER6trade microprocessor combines ultra-high frequency operation, aggressive power reduction, a highly scalable memory subsystem, and mainframe-like reliability, availability, and serviceability.

Abstract

The POWER6trade microprocessor combines ultra-high frequency operation, aggressive power reduction, a highly scalable memory subsystem, and mainframe-like reliability, availability, and serviceability. The 341mm 2 700M transistor dual-core microprocessor is fabricated in a 65nm SOI process with 10 levels of low-k copper interconnect. It operates at clock frequencies over 5GHz in high-performance applications, and consumes under 100W in power-sensitive applications.

Keywords

Computer ScienceEngineering