FPGA Implementations of Neural Networks – A Survey of a Decade of Progress
Lecture notes in computer sciencePublished 1 January 2003
Jihan Zhu, Peter Sutton
Citations196
SJR quartileQ2
SJR score0.35
SNIP0.55
Generate an AI Snapshot to get a quick, structured summary of this paper.
Study Snapshot
ObjectiveStudy objective
MethodsResearch methodology
PopulationPopulation studied
Sample sizeSample sizes
OutcomesStudy outcomes here
ResultsStudy results comes here
LimitationsResearch study limitations comes here
A concise AI-generated summary of the paper will appear here once you click Generate AI Snapshot.
TL;DR
A taxonomy for classifying FPGA implementations of artificial neural networks (ANNs) is provided and different implementation techniques and design issues are discussed.
Abstract
The ferst successful FPGA implementation [1] of artificial neural networks (ANNs) was published a little over a decade ago. It is timely to review the progress that has been made in this research area. This brief survey provides a taxonomy for classifying FPGA implementations of ANNs. Different implementation techniques and design issues are discussed. Future research trends are also presented.
Keywords
Computer ScienceEngineering
IEEE Journal of Solid-State CircuitsGANGLION-a fast field-programmable gate array implementation of a connectionist classifier
128 Citations1992Charles E. Cox, W. E. Blanz
The authors take advantage of the reprogrammability of the devices to automatically generate new custom hardware for each application of the classifier, which is a totally digital connectionist classifier.
IEEE Transactions on Neural NetworksFast neural networks without multipliers
127 Citations1993Michele Marchesi, G. Orlandi +2 more
Some test cases are presented, concerning MLPs with hidden layers of different sizes, on pattern recognition problems, to demonstrate the validity and the generalization capability of the method and give some insight into the behavior of the learning algorithm.
Density enhancement of a neural network using FPGAs and run-time reconfiguration
96 Citations2002J.G. Eldredge, Brad Hutchings
The run-time reconfiguration artificial neural network (RRANN) uses ran-time resurfacing to increase the hardware density of FPGAs and is a flexible realization of the time/space trade-off.
Neural NetworksOn the capabilities of neural networks using limited precision weights
93 Citations2002Sorin Drăghici
The paper presents an existence result which relates the difficulty of the problem as characterized by the minimum distance between patterns of different classes to the weight range necessary to ensure that a solution exists, which allows us to calculate a weight range for a given category of problems and be confident that the network has the capability to solve the given problems with integer weights in that range.
Back propagation simulations using limited precision calculations
87 Citations2002J.L. Holt, Troy Baker
Simulation results indicate that integer computation works quite well for the back-propagation algorithm, and the limited precision integer simulations performed as well as the floating point simulations.
Towards an FPGA based reconfigurable computing environment for neural network implementations
45 Citations1999Jinyang Zhu
It is argued that these computational characteristics of neural networks map nicely to fine-grained FPGA based reconfigurable computing architectures.
IEEE Transactions on Neural NetworksA new digital pulse-mode neuron with adjustable activation function
39 Citations2003Hiroomi Hikawa
A new pulse-mode digital neuron which is based on voting neuron is described, which provides adjustable nonlinear function, which resembles the sigmoid function.
Lecture notes in computer scienceFPGA implementation of an adaptable-size neural network
39 Citations1996Andrés Pérez-Uribe, Eduardo García Sánchez
This paper describes an FPGA implementation of the FAST (Flexible Adaptable-Size Topology) architecture, a neural network that dynamically changes its size, and applies this dynamic-structure FAST neural network to an image segmentation and recognition problem.
Lecture notes in computer scienceClassification and performance of reconfigurable architectures
31 Citations1995Steven A. Guccione, Mario J. Gonzalez
A model which unifies traditional instruction set architectures with reconfigurable architectures is proposed, which addresses issues of performance, programmability and scalability.
USING EMBEDDED PROCESSORS IN HARDWARE MODELS OF ARTIFICIAL NEURAL NETWORKS
21 Citations2001Denis F. Wolf, Roseli Aparecida Francelin Romero +1 more
An implementation that joins the software flexibility with the excellent hardware performance has been performed through the use of reconfigurable computing and embedded processors technologies.
Adapting constant multipliers in a neural network implementation
17 Citations2002P. James-Roxby, B.A. Blodget
This paper compares the use of run-time reconfiguration and read-only look-up tables, with a similar implementation using writable memories, for the multilayer perceptron neural network.
Lecture notes in computer scienceImplementing Kak Neural Networks on a Reconfigurable Computing Platform
11 Citations2000Jihan Zhu, George Milne
This paper shows that the Kak algorithm is hardware friendly and is especially suited for implementation in reconfigurable computing using fine grained parallelism and demonstrates that on-line learning with the algorithm is possible through dynamic evolution of the topology of a Kak neural network.
Theoretical and implementation aspects of pulse streams: an overview
10 Citations2003Leonardo Reyneri
An annotated overview of existing hardware implementations of artificial neural systems based on "pulse stream" modulations is presented, and the performances of the various techniques are compared both with each other, and with those of other analog computing systems.
Initial evolvability experiments on the CAM-brain machines (CBMs)
3 Citations2002Hugo de Garis, Andrzej Buller +5 more
This paper reports on the initial evolvability results obtained on CBM hardware, a specialised piece of programmable (evolvable) hardware that uses Xilinx XC6264 programmable FPGA chips to grow and evolve, at electronic speeds, 3D cellular automata based neural network circuit modules of some 1,000 neurons each.