System level diagnosis and wafer testing
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Abstract
This thesis consists of two related but s"lf-sustaining parts.In Part 1 a new diagnosability measure, l,' -I-diagnosability, is propos"d for interconnected systems.This new diagnosability assures that all faulty units, exoept for at most one, can be correctly id"ntifi"d in L)ne step, as long as the total number of faulty units does not excced t.Th" c1ass of tl -I-diagnosable systems is fully characterized.A polynomial algorithm is presented for dctermining the degree of tll.diagnosability for any given system.A polynomial diagnosis algorithm is also given for any tl -I-diagnosable systems.It is shown that the degree of tl -1 diagnosability could be twice as large as the degree of t-diagnosability for a given system.In Part II a probabilistic diagnosis algorithm is presented for constant degree structures such as grids.Il is shown that almost all f?ulty units can be correctly identified under a binomial failure distribution even when the probability of failure is rather high.The performance is very insensitive to yield variations under a negative binomial failure distributio-.The application of this algorithm to the prouction testing of chips and wafers is explored.A simple test structure is provided for wafer testing, which utilizes the test access port of each die to facilitate comparison testing.The diagnosis algorithm is localized and incorporated into the test structure to determine the status of each die.The scheme is unique in that it is shown to work well when faults are c1ustered and even when the yield is low.
