Adaptive Clock Gating Technique for Low Power IP Core in SoC Design

Published 1 May 2007

Xiaotao Chang, Mingming Zhang, Ge Zhang, Zhimin Zhang, Jun Wang

DOI10.1109/iscas.2007.378591

Citations40

TL;DR

An adaptive clock gating (ACG) technique which can be easily realized is introduced for the low power IP core design and can automatically enable or disable the IP clock to reduce not only dynamic power but also leakage power with power gating technique.

Abstract

Clock gating is a well-known technique to reduce chip dynamic power. This paper analyzes the disadvantages of some recent clock gating techniques and points out that they are difficult in system-on-chip (SoC) design. Based on the analysis of the intellectual property (IP) core model, an adaptive clock gating (ACG) technique which can be easily realized is introduced for the low power IP core design. ACG can automatically enable or disable the IP clock to reduce not only dynamic power but also leakage power with power gating technique. The experimental results on some IP cores in a real SoC show an average of 62.2% dynamic power reduction and 70.9% leakage power reduction without virtually performance impact.

Keywords

Computer ScienceEngineering

Computer Architecture: A Quantitative Approach

9,536 Citations1989John L. Hennessy, David A. Patterson

This best-selling title, considered for over a decade to be essential reading for every serious student and practitioner of computer design, has been updated throughout to address the most important trends facing computer designers today.

Wattch

2,559 Citations2000David Brooks, Vivek Tiwari +1 more

Wattch: a framework for architectural-level power analysis and optimizations

1,124 Citations2002David Brooks, Vivek Tiwari +1 more

Power considerations in the design of the Alpha 21264 microprocessor

370 Citations1998M.K. Gowan, Larry Biro +1 more

The 21264 is a third generation Alpha microprocessor implementation, containing 15.2 million transistors and operating at 600 MHz, and the electrical design of the power, ground, and clock networks is presented.

Power and energy reduction via pipeline balancing

166 Citations2001R. Iris Bahar, Srilatha Manne

Clock-tree power optimization based on RTL clock-gating

105 Citations2003Monica Donno, Alessandro Ivaldi +2 more

This paper presents a methodology that, starting from an RTL description, automatically generates a set of constraints for driving the construction of the clock tree by the clock synthesis tool, fully integrated into an industry-strength design flow.

Power and energy reduction via pipeline balancing

86 Citations2002R.I. Bahar, Srilatha Manne

This work proposes an architectural solution to the power problem that retains performance while reducing power, and detail instruction queue design and energy savings based on an extension of the Alpha 21264 processor.

IEEE Transactions on Very Large Scale Integration (VLSI) SystemsDCG: deterministic clock-gating for low-power microprocessor design

58 Citations2004Hai Li, Swarup Bhunia +3 more

A deterministic clock-gating (DCG) technique which effectively reduces clock power in high-performance processors by applying DCG to execution units, pipeline latches, D-cache wordline decoders, and result bus drivers.

SoC Leakage Power Reduction Algorithm by Input Vector Control

8 Citations2005Xiaotao Chang, Dongrui Fan +2 more

Experimental results on large combinational circuits of ISCAS85 benchmark and a real general-purpose SoC show this algorithm can accelerate calculation over three times with acceptable accuracy (error about 0.14%).

An Effective IP Reuse Methodology for Quality System-on-Chip Design

7 Citations2005S. Sarkar, Sanjay M. Shinde +1 more

The methodology that is described consists of enhancing the IPs for meeting the desired goals, validating the changes and controlling its version in the design database, required to integrate three mission critical IPs developed by the customer.